There is known a latch circuit which comprises a differential circuit as a basic element circuit of logic circuits used in a variety of semiconductor integrated circuits.
FIG. 1 illustrates a circuit diagram of a conventional general latch circuit. As illustrated in FIG. 1, conventional latch circuit 50a comprises a vertical stack for a total of three stages which include a differential circuit (a differential pair composed of transistors Q51 and Q52 and the like) stage for reading data and a differential circuit (a differential pair composed of transistors Q53 and Q54 and the like) stage for holding data; a differential circuit (a differential pair composed of transistors Q55, Q56 or the like) stage which receives a clock signal and which functions to switch a current to an upper stage of the differential circuit; and a stage of transistor Q57, at a lower stage than that, for regulated current source.
Thus, the foregoing configuration requires a higher supply voltage, as compared with other basic circuit elements, and constitutes an impediment to a total reduction in voltage and power consumption when the logic circuit is integrated into one chip or a modular form together with other functional circuit blocks. Consequently, a large challenge has been to restrain power consumption of the latch circuit (see, for example, JP-A-63-86611 and JP-A-2-21717).
As a measure to reduce voltage for such a latch circuit, a circuit as illustrated in FIG. 2, for example, is proposed in JP-A-63-86611 and JP-A-2-21717.
FIG. 2 illustrates a circuit diagram of a latch circuit which has two differential circuits arranged in parallel (parallelly arranged latch circuit). In latch circuit 50b illustrated in FIG. 2, a current switching transistor (Q58), which is applied with a clock signal, has an emitter terminal connected to a common emitter terminal of a differential circuit (composed of transistors Q51 and Q52 and the like), while a current switching transistor (Q59) has an emitter terminal connected to a common emitter terminal of a differential circuit (composed of transistors Q53 and Q54 and the like).
In such a circuit configuration, only if logical amplitudes are set high for the current switching transistors (Q58, Q59) will a current to the differential circuits be shut off when the clock signal is at a high level because current from a regulated current source flows through the current switching transistors (Q58, Q59). On the other hand, when the clock signal is at a low level, the current from the regulated current source flows through the differential circuits.
In the foregoing manner, in the circuit illustrated in FIG. 2, a latching operation is implemented by switching a current in synchronization with the clock. In this way, the need to arrange a vertical stack of differential circuits is eliminated, thus making it possible to reduce the voltage.
However, the conventional circuit has problems shown below.
So that latch circuit 50b as illustrated in FIG. 2 operates correctly, a strong influence on the switching operate under control of the clock signal must be increased, as compared with data signals, such that currents from current source transistors (Q60, Q61) will always flow through the current switching transistors (Q58, Q59) when the clock signal is at a high level. This can be made possible by setting the size of the current switching transistors (Q58, Q59) larger than the transistors (Q51, Q52, Q53, Q54) which made up the differential circuits. As the size of the transistors (Q58, Q59) is larger, the strong influence of the clock signal is increased. However, the use of excessively large transistors would result in a degradation in high-speed performance and an increase in consumed current.
Thus, there are limitations in the size of the current switching transistors (Q58, Q59) per se, so that it is actually difficult to completely have a strong influence on the current switching transistors (Q58, Q59). For this reason, even when the clock signal is at a high level, part of the current supplied from a current source will leak to the differential circuits.
FIG. 3 is a diagram representing the relationship between current I1 which flows into a current switching transistor and current I2 which flows into a differential circuit from a current source in a parallelly arranged latch circuit when it is in operation. It can be seen that when the current switching transistor (Q58) turns on to allow I1 to flow, current I2 to the differential circuit, which should be essentially shut off, is not completely eliminated (portion A in the figure), but a leak current flows. A reduction in potential level of a data signal due to this leak current can lead to a degradation in output waveform and the like, if the reduction is not negligible with respect to a logical amplitude of data.
Also, irrespective of the type of circuit forms that make up latch circuits, generally, when an attempt is made to reduce a supply voltage, VCE distributed to each transistor cannot but be reduced. For this reason, an optimal operating condition cannot always be selected for high frequency performance of a device, thus leading to difficulties in ensuring high-speed performance. As a measure to improve high speed performance, an inductor keeping technique is effective.
FIG. 4 illustrates a circuit diagram of a parallelly arranged latch circuit which has improved high-speed performance. To improve high-speed performance, a wire is extended on a collector side of a differential circuit (transistors Q51 and Q52 or transistors Q53 and Q54), or a spiral inductor is disposed on the collector side. Based on parallel resonance of inductance L produced herein and capacitance C of a transistor connected at the next stage, the gain is increased in a high frequency region to improve high-speed performance.
Incidentally, in regard to a parallelly arranged latch circuit, the improvement in high-speed performance is desirable for the current switching transistors (Q58, Q59) as well, except for the differential circuit. However, in the example of FIG. 4, the collectors of the current switching transistors (Q58, Q59) are simply connected to a high potential power supply terminal through resistors, but circuits including transistors are not at all connected, so that a capacitive component in this portion is nothing but an extremely small stray capacitance. Thus, for giving rise to gain peaking based on parallel resonance in a desired high frequency region, an extremely large wiring inductance is required, thereby making improvement in high-speed performance unrealistic due to restraints in the chip area.
A large number of latch circuits are used in a variety of functional circuits. FIG. 5 is a diagram illustrating circuit blocks of 2:1 MUX. As illustrated in FIG. 5, 2:1 MUX comprises circuit elements such as master/slave flip-flop circuit (MS-F/F) 71, master/slave/master flip-flop circuit (MSM-F/F) 72, selector circuit (SELECTOR) 73, and the like. Each of these circuit elements is built using latch circuits. Here, since complementary clock signals are supplied to each circuit element, the clock signal is branched into a large number of paths. For this reason, a buffer circuit is required in each branch for signal amplification, resulting in an increased number of circuits and increased power consumption. Therefore, in integrated functional circuits, it is necessary not only to reduce power consumption of respective latch circuits, but also to reduce the number of circuits such as buffer circuits (BUF).